Integrated circuit Field Effect Transistors (FETs), often referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Metal Insulator Semiconductor Field Effect Transistors (MISFETs), insulated gate field effect transistors, or simply as MOS/MIS devices, are widely used in integrated circuit logic, memory, processor, analog and/or other integrated circuits for consumer, commercial and/or other applications. As the integration density of integrated circuit field effect transistors continues to increase, the size of the active region and the channel length thereof may continue to decrease. With the reduction in the channel length of the transistor, the influence of the source/drain region upon the electric field or potential in the channel region may become considerable, giving rise to so called “short channel effects”. Moreover, with the scaling down of the active areas, the channel width may decrease, which may also increase the threshold voltage of the device and/or give rise to other so-called “narrow width effects”.
Vertical pillar transistors have been proposed in attempts to reduce these and/or other effects. In a vertical pillar transistor, a vertical channel may be provided in a pillar that extends from an integrated circuit substrate. A vertical pillar transistor is described in U.S. Pat. No. 5,480,838 to Mitsui, entitled “Method Of Manufacturing A Semiconductor Device Having Vertical Transistor With Tubular Double-Gate”. FIG. 2 of Mitsui is reproduced as FIG. 1 herein. As stated in the Abstract of Mitsui, a semiconductor device allowing control of its threshold voltage without requiring change in the materials of its gate electrodes and suitable for high density integration is disclosed. The semiconductor device includes a p type monocrystalline silicon substrate 1 having a cylindrical portion with inner and outer surfaces and extending in a vertical direction. A first gate electrode 8 and a second gate electrode 10 are disposed at the inner surface and the outer surface of the cylindrical portion 2, respectively. A source/drain region 5 is formed on the top end of the cylindrical portion 2, while a source/drain region 3 is formed on the inner bottom surface of the cylindrical portion 2. Therefore, the cylindrical portion 2 can be utilized as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can easily be controlled by applying separate voltages to the two gate electrodes, the first electrode and the second electrode.
Another vertical pillar field effect transistor is described in U.S. Pat. No. 6,015,725 to Hirayama, entitled “Vertical Field Effect Transistor and Manufacturing Method Thereof”. FIG. 2 of Hirayama is reproduced as FIG. 2 herein. As stated in the Abstract of Hirayama, a vertical field effect transistor 1 and a method of manufacturing thereof are disclosed, in which a buried layer 3 of a conduction type opposite to that of a substrate 2 is formed to a predetermined depth in the substrate 2 by ion implantation. The bottom of recess 2a for forming a protrusion 2b on the substrate 2 is located within the corresponding one of the buried layer 3. The width of the recess 2a is set smaller than the width of the buried layer 3. The surface of the protrusion 2b and the bottom of the recess 2a are formed with impurities regions 4a, 4b; 5a, 5b constituting a source and a drain, respectively. A channel length L of the channel region formed on the sidewall of the protrusion 2b is defined by the distance between the buried layer 3 and the impurities regions 5a, 5b on the surface of the protrusion 2b. 
Unfortunately, vertical pillar transistors as described above may also exhibit Gate-Induced Drain Leakage (GIDL), which may also reduce the performance of the vertical pillar transistor.